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Nintendo 64: Difference between revisions
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[[File:Nintendo-64.jpg|thumb|right|320px|A Nintendo 64 console with a gray controller attached.]] | |||
''[https://en.wikipedia.org/wiki/Nintendo_64 See this page on Wikipedia]'' | ''[https://en.wikipedia.org/wiki/Nintendo_64 See this page on Wikipedia]'' | ||
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==Hardware== | ==Hardware== | ||
The N64 contains the following main components: | The N64 contains the following main components:<br> | ||
- A VR4300 (R4300i) MIPS III CPU clocked at 93.75 MHz by default | - A VR4300 (R4300i) MIPS III CPU clocked at 93.75 MHz by default<br> | ||
- The Reality Coprocessor (RCP), which handles graphics and audio and is made up of the Reality Display Processor (RDP) and Reality Signal Processor (RSP), the latter of which is an R4000-based vector processor | - The Reality Coprocessor (RCP), which handles graphics and audio and is made up of the Reality Display Processor (RDP) and Reality Signal Processor (RSP), the latter of which is an R4000-based vector processor<br> | ||
- 4.5 MB of RDRAM (9 MB with Expansion Pak); the RAM is on a 9-bit bus but the 9th bit is only available to the RCP, making it only 4 MB (8 MB with Expansion Pak) for the CPU | - 4.5 MB of RDRAM (9 MB with Expansion Pak); the RAM is on a 9-bit bus but the 9th bit is only available to the RCP, making it only 4 MB (8 MB with Expansion Pak) for the CPU<br> | ||
- The Peripheral Interface chip (PIF), which verifies cartridges and interfaces the CPU with peripherals such as [[N64 Controller|controllers]], cartridge [[EEPROMs|EEPROMs]], and the reset button | - The Peripheral Interface chip (PIF), which verifies cartridges and interfaces the CPU with peripherals such as [[N64 Controller|controllers]], cartridge [[EEPROMs|EEPROMs]], and the reset button<br> | ||
==Boot Process== | ==Boot Process== | ||
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When the reset button is pressed, the PIF sends a "pre-NMI" interrupt to the CPU, and 0.5s later sends the NMI that resets the console. Letting the CPU know about the reset in advance allows games to add handlers for resets, such as SM64's reset animation. | When the reset button is pressed, the PIF sends a "pre-NMI" interrupt to the CPU, and 0.5s later sends the NMI that resets the console. Letting the CPU know about the reset in advance allows games to add handlers for resets, such as SM64's reset animation. | ||
When the NMI occurs, RAM is not cleared. In SM64, the bss of the main segment is cleared, but not the bss of other segments (I think?). | When the NMI occurs, RAM is not cleared. In SM64, the bss of the main segment is cleared to 0 on boot, but not the bss of other segments (I think?). | ||